Semiconductor devices, such as semiconductor memory devices, can be designed so as to be capable of supporting different supply voltages, depending on the intended application. For example, dual-power-supply semiconductor devices (such as, for example, flash memory ICs) can operate with either a first, higher supply voltage (e.g., 3V) or a second, lower supply voltage (e.g., 1.8V).
Operation at a lower supply voltage is for example typical of battery-powered systems, and allows reducing the power consumption.
In both cases, the (lower or higher) supply voltage is fed to the internal circuitry of the semiconductor device, through supply-voltage distribution lines, which are adapted to distribute the supply voltage through the device.
In particular, a known design rule provides for having supply-voltage distribution lines for distributing the supply voltage to the device's core circuitry, comprising key circuital structures adapted for performing the desired tasks (like, in the case of memory devices, memory cells row and column selectors, sense amplifiers, control logic controlling the memory device operation), which are distinct from supply-voltage distribution lines for distributing the supply voltage to input/output circuits, like input/output buffers. By this measure, it is possible to reduce the risk that the operation of the core circuitry is affected by noise on the supply voltage produced by the switching of the input/output circuits. In other words, dedicated supply-voltage distribution lines are used for the core circuitry and the input/output circuits, for decoupling the disturbs occurring during the input/output buffers operation from the remaining circuitry of the semiconductor device.
In order to reduce power consumption, the internal circuitry, particularly the core circuitry of dual-power-supply devices is typically designed to operate with a supply voltage that is lower than the first, higher supply voltage (for example, the internal circuitry of the semiconductor device voltage may be designed to operate with an internal supply voltage of 2.3V, which is intermediate between the first, higher supply voltage and the second, lower supply voltage). For down-converting the external, higher supply voltage into the (lower) internal voltage, a Voltage Down-Converter “VDC” is provided for, which is able to lower the voltage (e.g., starting from the external voltage of 3V, the VDC generates the internal voltage of 2.3V). The VDC has also the function of stabilizing the internal supply voltage of the semiconductor device.
On the other hand, those parts of the circuitry of the semiconductor device that, like input/output buffers, are used for interfacing the semiconductor device with the external environment (typically a system bus), need to be supplied at either the first, higher supply voltage, or to the second, lower supply voltage, depending on the environment in which the semiconductor device is inserted. Voltage-level adapters (shifters) are provided for interfacing the core circuitry with the input/output circuits.
When the semiconductor device is employed in low-supply voltage applications, the internal circuitry of the semiconductor device should be supplied by a supply voltage equal to the external supply voltage. A voltage switch is provided for the electrical connection between the supply-voltage distribution line that receives (from the semiconductor device terminals) the externally supplied supply voltage and the supply-voltage distribution line that distributes the supply voltage to the core circuitry; the VDC is in this case kept off, and bypassed by the voltage switch.
The dual-power-supply semiconductor device is typically configured for either a lower-voltage application or a higher-voltage application during the testing, for example by burning a fuse in a control structure that controls the activation of the VDC or, in alternative, of the voltage switch.
Typically, the voltage switch is implemented by a MOS transistor, particularly of p-type conductivity (i.e., a PMOS), which is connected between the semiconductor device terminals that, in operation, are connected to the supply-voltage distribution line that receives the externally supplied supply voltage and the supply-voltage distribution line distributing the supply voltage to the core circuitry, and has a control (i.e. a gate) terminal receiving the control signal. When, as a consequence of the semiconductor device configuration during the testing, the PMOS transistor is turned on, the low supply voltage received from the supply-voltage distribution line is fed to the core circuitry.
The voltage switch has a resistance (the PMOS transistor on resistance) that inevitably causes a voltage drop across it. Thus, the actual internal supply voltage, which is fed to the core circuitry, is often lower than the external low supply voltage.